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VSORA is a French fabless semiconductor company delivering ultra-high-performance AI inference solutions for both data centers and edge deployments. Our proprietary architecture achieves exceptional implementation efficiency, ultra-low latency, and minimal power draw - dramatically cutting inference costs across any workload. Fully programmable and agnostic to both algorithms and host processors, our chips serve as versatile companion platforms. A rich instruction set lets them seamlessly handle pure AI, pure DSP, or any hybrid of the two, all without burdening developers with extra complexity. To streamline development and shorten time-to market, VSORA embraces industry standards: our toolchain is built on LLVM and supports common frameworks like ONNX and PyTorch, minimizing integration effort and customer cost. Based in the outskirts of Paris (Headquarted in Meudon - France), the company was founded in 2015 by a team of highly qualified and accomplished AI/DSP experts and entrepreneurs (with one subsidiary in the US and rep offices around the world), validated its core technology end of 2025 and is about to initiate its commercial ramp up with a view to reach €500m+ in the next 2 years.

Key Responsibilities

• Own and drive RTL-to-Post CTS integration flow for large hierarchical blocks and top-level SoC
• Manage DFT integration at block and top level, including scan stitching, and test mode implementation
• Integrate multiple IPs and subsystems (including high-speed PHYs and controllers such as UCIe, PCIe, HBM), ensuring test connectivity and timing constraints.
• Define and manage hierarchical integration strategies, including partitioning, floorplanning guidance, and interface budgeting (timing, congestion, power, and test)
• Develop, maintain, and validate timing and test constraints (SDC), including multi-mode multi-corner (MMMC) scenarios covering functional and test modes
• Drive timing closure across hierarchy, including setup/hold fixing and ECO implementation post-CTS, with full awareness of test paths and scan impact
• Ensure DFT structures are correctly implemented and preserved through place & route (scan chains, compression logic, test points, boundary scan)
• Collaborate closely with embedded software and test engineers to validate functional and test patterns
• Handle integration of test features such as scan compression, MBIST, boundary scan (IEEE 1500, IEEE 1687)
• Analyze STA reports in both functional and test modes.
• Develop automation scripts (Tcl, Python, Bash, CMake) to improve integration and DFT flow robustness
• Ensure traceability of flow evolution with Git

Requirements and Skills

• Master’s degree in Electrical Engineering, Microelectronics, or related field
• 3–5 years of relevant experience in digital design integration, physical design, or DFT integration

Proven expertise in:

• RTL-to-GDSII flow knowledge (synthesis, place & route, CTS, post-CTS optimization)
• DFT integration and implementation (scan chains, compression, MBIST, Interface IP BIST)
• Hierarchical design integration and large SoC assembly
• Static Timing Analysis (STA) including test modes and constraints (SDC, MMMC)
• Hands-on experience with industry-standard EDA tools
• Experience in one or more of the following domains is highly appreciated:
• ATPG flow, test coverage analysis, and pattern validation
• Integration of high-speed interfaces (PCIe Gen5/6, UCIe, HBM or equivalent)
• Clock tree design including scan clocking and test clock strategies
• Low-power design techniques (UPF/CPF)
• Signal integrity and cross-talk aware timing closure
• Strong scripting and automation skills (Tcl, Python, CMake)
• Knowledge of Git philosophy and usage

Additionally, the following skills can be a plus:

• Familiarity with large-scale AI/compute SoC architectures
• Experience with chiplet-based design and advanced packaging (2.5D/3D, interposers)
• Knowledge of silicon bring-up, test debug, and yield analysis
• Experience working in highly collaborative, cross-functional environments

Office locations :

This position can be based in either of our offices, depending on your location:

Grenoble:

CEMOI A110

12 rue ampère

38000 Grenoble

Paris area:

VSORA

15 Rue Jeanne Braconnier

92360 Meudon